Central processing units (CPUs) are widely used in personal computers, and embedded applications, such as videos, graphics, wireless communications, and the like, are key components of many system-on-chip (SoC) applications. A common requirement to the design of CPUs is to increase their energy efficiency. The energy efficiency may be measured using a performance to power ratio, which may be, for example, million instructions per second (MIPS)/mW or million operations per second (MOPS)/mW. MIPS are units for expressing performance and indicate how many millions of instructions the CPU can process per second.
In general, power consumption is proportional to the square of an applied power supply voltage. A decrease in the power supply voltage is hence the most effective way to reduce power consumption. In a whole system, the clock frequency of a CPU is the highest among all the necessary building blocks in order to meet application requirements. As a result, power consumption and heat generation are also the highest among all building blocks. Accordingly, reducing a CPU's power consumption is the most effective way to reduce the system's overall power consumption. However, reducing the power supply voltage of a CPU may result in the speed of the CPU being reduced. Dynamic power supply control thus comes into play. Known dynamic power supply control techniques include dynamic voltage and frequency scaling (DVFS) techniques and adaptive voltage scaling (AVS) techniques, which have been used to improve energy efficiency. DVFS and AVS techniques have the ability to dynamically reduce power supply voltage to satisfy different operating conditions and different operation requirements. For example, if it is determined that a low performance is required or the external environment allows for a reduced power supply voltage, the power supply voltage provided to the CPU is reduced. Otherwise, the power supply voltage is maintained or even increased.
The DVFS and AVS techniques, however, suffer from limitations in both SoC and system-in-package (SiP) applications. For example, when integrated on SoC applications, a CPU may include embedded memories, such as level-1 cache memories. Referring to FIG. 1, CPU 100 includes memory block 102 and core block 104. Core block 104 is built in libraries and stored as “standard cells.” These libraries contain large numbers of pre-designed circuits (also referred to as basic building blocks). Voltage regulator module 106 generates power supply voltage VDD and provides power supply voltage VDD to CPU 100. DVFS/AVS system 108 determines the magnitude of, and controls voltage regulator module 106 to generate, the desirable power supply voltage VDD.
The magnitude of power supply voltage VDD must be high enough to satisfy the Vcc_min requirement of memory block 102, wherein Vcc_min is the minimum power supply voltage needed to reliably perform read and write operations on memory block 102. Unfortunately, the Vcc_min is typically greater than the minimum operation voltage of core block 104. This means that a reduction in the power consumption of core block 104 is capped by the requirement of memory block 102.